The present invention relates to the field of bus switches. More particularly, the present invention relates to a crossbar bus network including a crossbar switch circuit comprising a communication bus ring.
Efficient communication of information is critical to the advancement of a modern society. For example, electronic technologies that require significant amounts of data to be communicated at a rapid pace are utilized in a growing number of diverse applications to accomplish useful tasks. Advances in electronic devices for processing and transmitting electrical signals have increased the demand for even greater data communication bandwidth in a variety of areas, including telecommunications and computer systems.
Computer systems are used to perform a wide variety of tasks and play an important role in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. In the past, computers were primarily applied to rather mundane, repetitive numerical and/or textual tasks involving spread sheets and word processors. More recently computers are being utilized in more advanced, versatile, and sophisticated applications. A partial list of areas impacted by these applications include the generation of special effects for movies, realistic computer-generated three-dimensional graphic images and animation, real-time simulations, video teleconferencing, Internet-related applications, computer games, telecommuting, virtual reality, high-speed databases, real-time interactive simulations, medical diagnostic imaging, etc. The usefulness of a computer in performing some of these tasks is largely determined by the speed at which the computer performs.
There are a number of factors that affect the speed at which a computer performs. For example the capacity and speed of a central processing unit has a notable impact on a computer""s performance. Another factor that has a significant influence on a computer""s performance is the data communications bandwidth, that is the speed at which the communications infrastructure permits the various components of a computer system to communicate with one another. One of the major bottlenecks in attaining faster computer systems with greater bandwidth is prior art bus architectures.
Typically a xe2x80x9cbusxe2x80x9d is comprised of one or more wires that electrically interconnect components of a computer system, such as semiconductor chips and input/output devices. Virtually all of today""s computer systems use this same type of bus scheme. The bus conducts electrical signals that enable various components in the computer system to communicate with each other. The computer system components often use the bus to convey digital data, address information for specifying the destination of the data, control signals, and timing/clock signals. The components utilizing the bus for communications are usually attached to the bus in a linear configuration and are subject to an arbitration process. At any given time the arbitration process permits only one component to transmit a message to one other component coupled to the bus.
FIG. 1 shows a schematic of a typical prior art computer graphics system 100. Computer graphics system 100 comprises a central processing unit (CPU) 101, a main memory 102, graphics controller 103, frame buffer 104, mass storage device 105, keyboard controller 106, keyboard 108, printer 109 and display monitor 110, all of which are coupled to bus 107. CPU 101 handles most of the control and data processing. Main memory 102 provides a convenient method of storing data for quick retrieval by CPU 101. Graphics controller 103 processes image data in pipelined stages. Frame buffer 104 stores pixel parameter values. Mass storage device 105 stores data associated with multiple images and applications. Keyboard controller 106 controls keyboard 108, which operates as an input device. Printer 109 prints hard copies of graphical images and display monitor 110 displays graphical images.
Bus 107 enables components coupled to the bus to communicate with each other by carrying electrical signals between them. For instance, CPU 101 may send a signal over bus 107 to retrieve certain data stored in main memory 102. Upon receipt of this read request, main memory 102 sends the requested data back via bus 107 to CPU 101. Once the CPU is finished processing the data, a signal can be sent again via bus 107 to graphics 3controller 103 and then onto frame buffer 104 and display monitor 110 resulting in the processed data being displayed. In FIG. 1 all of the components share a common bus 107 and they all rely on the arbitration process to meet their individual communication needs.
Relying on this prior art bus architecture and its arbitration process means that only one component can have access to the bus at any given time for a one way communication, regardless of communication requirements of any other components. If one component is utilizing bus 107 a significant delay can occur in meeting the individual communication needs of the other components. For example, if bus 107 is currently busy transmitting signals between devices (e.g. CPU 101 and printer 109), then all the other devices coupled to that bus must wait until that transaction is complete and bus 107 again becomes available. Once the bus becomes available the remaining devices are subject to an arbitration process which determines whether a component gains access to bus 107. The arbitration process and bus architecture of the prior art is not able to keep pace with the skyrocketing craving for increased bus access and bandwidth.
Increasing the bus width introduces severe detrimental xe2x80x9cside effectsxe2x80x9d that significantly impact the overall efficiency of the computer system. The increase in bus width consumes valuable space on already densely packed and overcrowded printed circuit boards. Additional pins are required on each of the semiconductor chips connected to the bus in order to match the increase in bus width. These additional pins significantly increase the size of the chips and it becomes more difficult to fit these chips onto the printed circuit boards. Furthermore, the increase in the chip""s overall size and number of pins adversely affects the costs of manufacturing chip packages. For the typical computer system, increasing the bus width from 64 bits up to more desirable bandwidth capabilities (e.g., 128 bits wide) is impractical.
Increasing the frequency also increases the probability that undesirable results could significantly impact the operation of the computer system. The physics associated with implementing long sets of parallel wires with multiple electrical signals produces a wide range of problems such as impedance, mismatches, reflections, crosstalk, noise, non-linearities, attenuations, distortions, timing issues, etc. These problems become even more severe as the frequency increases. Utilizing higher frequencies requires fine tuning extremely tight tolerances, utilizing exotic micro-chip layouts, and extensive testing, which makes higher frequency computers extremely difficult to reliably mass produce and impractical. As a practical matter the highest attainable frequency in a typical computer systems is approximately 33-50 Mhz. Given a 64 bit bus running at 50 Mhz, the highest attainable data rate would be approximately 400 Mbytes per second. The data rate demands imposed by desirable new applications exceeds these limitations.
Thus, there is a great need for a bus architecture that provides increased data communications bandwidth in a reliable, cost effective, and extremely efficient manner. The bus should be capable of providing high speed data communications with minimal latency problems. The bus architecture should be adaptable to wide variety of systems and have the ability to satisfy the data communication bandwidth requirements of the diverse components and unique devices that may be incorporated in a computer system.
The present invention is an efficient system and method that increases the speed at which bits of data can be conveyed (e.g., increased bandwidth) in an electronic system by permitting multiple components to effectively communicate with one another at the same time. The present invention involves a multi-link architecture that is capable of providing high speed data communications with low latency characteristics in a reliable, cost effective, and efficient manner. The present multi-link architecture is adaptable to various data communications applications (such as networks and computer systems) and can satisfy the unique data communication bandwidth requirements of a wide variety of devices in a network system.
In one embodiment a crossbar bus network of nodes is coupled to a crossbar switch circuit that operates as a communications hub routing messages simultaneously to and from the nodes over multiple links. The crossbar switch circuit includes a dedicated communications bus ring adapted to transmit data such as programmed input/output (PIO) messages between components of said crossbar switch circuit. The communications bus ring can be used for secondary high latency data communications thereby freeing switching matrix links of the crossbar switch circuit for simultaneous unimpeaded important low latency data communications to the same device.